1. Field of the Invention
The present invention relates to an electronic control device including an arithmetic device such as a microcomputer having a watchdog timer circuit, and more specifically relates to technology for monitoring a microcomputer for failures.
2. Description of the Related Art
Microcomputers have been designed to have a mode (high-speed mode) in which they operate at high-speed clock during normal operation, and a mode (power-saving mode) in which they operate at a speed lower than the high-speed clock or terminate the operation, in order to reduce power consumption. An example of technology for monitoring such microcomputers for failures is disclosed in Japanese Patent Application Publication No. 2004-326629. The failure monitoring device disclosed in Japanese Patent Application Publication No. 2004-326629 includes a watchdog timer monitoring section which detects a failure during normal operation of the microcomputer, and a stand-by monitoring section which detects a failure during stand-by operation of the microcomputer, both of which are provided external to the microcomputer. Both monitoring sections monitor watchdog pulses output from the microcomputer. During normal operation of the microcomputer, the watchdog pulses are output with a certain periodicity. During a failure, the periodicity is lost. During stand-by operation of the microcomputer, the watchdog pulses are normally not output. However, there may be cases where the watchdog pulses are output during failure. Thus, a failure during normal operation and stand-by operation can be detected by monitoring the watchdog pulses.
However, since the failure monitoring device has a configuration in which two different monitoring sections are provided external to the microcomputer, the size of the device becomes large, resulting in high cost.